
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:23:25 04/23/2012
-- Design Name:   captador
-- Module Name:   C:/Xilinx92i/captador/testbench_captador.vhd
-- Project Name:  captador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: captador
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench_captador_vhd IS
END testbench_captador_vhd;

ARCHITECTURE behavior OF testbench_captador_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT captador
	PORT(
		PILA_OUT : IN std_logic_vector(9 downto 0);
		OFFSET : IN std_logic_vector(7 downto 0);
		JUMP_ADDRESS : IN std_logic_vector(9 downto 0);
		PC_IN : IN std_logic_vector(9 downto 0);
		INT_RET : IN std_logic_vector(9 downto 0);
		IS_BRANCH : IN std_logic;
		BRANCHOP : IN std_logic_vector(1 downto 0);
		IS_RETI : IN std_logic;
		IS_SUB_RET : IN std_logic;
		IS_JUMP : IN std_logic;
		IS_INTR : IN std_logic;          
		PC_NEW : OUT std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL IS_BRANCH :  std_logic := '0';
	SIGNAL IS_RETI :  std_logic := '0';
	SIGNAL IS_SUB_RET :  std_logic := '0';
	SIGNAL IS_JUMP :  std_logic := '0';
	SIGNAL IS_INTR :  std_logic := '0';
	SIGNAL PILA_OUT :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL OFFSET :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL JUMP_ADDRESS :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL PC_IN :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL INT_RET :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL BRANCHOP :  std_logic_vector(1 downto 0) := (others=>'0');

	--Outputs
	SIGNAL PC_NEW :  std_logic_vector(9 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: captador PORT MAP(
		PILA_OUT => PILA_OUT,
		OFFSET => OFFSET,
		JUMP_ADDRESS => JUMP_ADDRESS,
		PC_IN => PC_IN,
		INT_RET => INT_RET,
		IS_BRANCH => IS_BRANCH,
		BRANCHOP => BRANCHOP,
		IS_RETI => IS_RETI,
		IS_SUB_RET => IS_SUB_RET,
		IS_JUMP => IS_JUMP,
		IS_INTR => IS_INTR,
		PC_NEW => PC_NEW
	);




	tb : PROCESS
	BEGIN

		wait for 100 ns;
		IS_BRANCH <= '1';
		JUMP_ADDRESS <= "0101010101";
		BRANCHOP <= "00";
		PC_IN <= "0000000001";
		OFFSET <= "00000001";
		IS_JUMP <= '1';
		-- PC_NEW deberia ser igual que el JUMP_ADDRESS: 0101010101
		wait for 100 ns;
		IS_BRANCH <= '0';
		BRANCHOP <= "00";
		PC_IN <= "0000000001";
		OFFSET <= "00000001";
		IS_JUMP <= '0';
		IS_SUB_RET <= '0';
		IS_RETI <= '0';
		IS_INTR <= '0';
		-- PC_NEW deberia ser tempSumador
		wait for 100 ns;
		IS_BRANCH <= '1';
		BRANCHOP <= "00";
		PC_IN <= "0000000001";
		OFFSET <= "00000001";
		IS_JUMP <= '1';
		-- PC_NEW deberia ser igual que el JUMP_ADDRESS: 0101010101
		wait; -- will wait forever

	END PROCESS;

END;
